CMPH 227 Logic Analyzer

Stefan Myroniuk,
and
Chris Bontje

SAIT





Introduction
The digital logic analyzer is a device that is used by many individuals in the electronics industry to help troubleshoot problems with digital circuitry that otherwise would have to be manually tested. The logic analyzer is manufactured by �Tektronix�, a company that produces test instruments for digital and analogue circuits. Although the model may seem bulky and slow at first, the capabilities greatly outweigh those of newer, more portable logic analyzers. These capabilities will be discussed in a later section.

Capabilities
In operation, the basic operation of the logic analyzer works much like an oscilloscope, with several input probes and a display unit that shows the activity on the probe. The main difference that separates this machine from an oscilloscope is the fact that it has many more input channels, and memory capabilities that allow the user to view the activity of several waveforms with relation to each other. Typically, this operation would be used to find faults in circuits (because, after all, if a circuit is working correctly, why would you check it?) which can range in a multitude of options. The logic analyzer can detect the following types of faults in digital circuits:

In our digital logic course, we have so far covered the following faults: no data, glitches, spikes and races. These will appear in the output display, if they are present in the circuit.

Components
There are a few main components to the Tektronics Digital Logic Analyzer, which must be known in order to use the device effectively. These devices, along with a short description, are as follows:
The main CPU unit is the large case on wheels, which has the diskette drives and drawers on the front. The CPU controls the main configuration, collecting of data, and processing of data. There several output and input ports on the back of the unit, such as where the POD�s and the monitor are plugged in. There is also primary and secondary storage options for the unit (hard disk and floppy disk, respectively), which store your configuration options and output results while you use them.
The display device on top of the main CPU, the monitor is our primary output peripheral on the logic analyzer. This monitor is a simple CRT type, with 16-color display capabilities, and a few settings adjustment on the front of the unit (contrast, etc.). It acts independently of the logic analyzer, much unlike a computer monitor, �Tektronix� monitor has a display adapter built-in to it. The main effect of this condition, is that when you power-down the monitor when the machine is on, the display will not come back on when it is re-powered, unlike a computer monitor.
This is simply a keyboard, with a few extra keys on it, for added functionality with the logic analyzer. The most significant item you will notice on the keyboard, is the built-in �mouse� located at the upper-left hand corner of the keyboard. This �mouse� is essentially what will be used to navigate around your resultant waveforms. The next key you will notice is the �Select Menu� key, which is the main navigational key for the logic analyzer �OS�. (Whatever menu your in, you can always return to the main menu by pressing this key.) There are a few more keys that will vary from a standard computer keyboard, but they are not essential to the operation of the logic analyzer.
This is the add-on device that plugs into one of the input ports in the back of the main CPU unit. It has 96 data input channels, divided into the following classifications:

Address � 4 sections * 8 channels (labeled A0-A3) 32 channels
Control � 2 sections * 4 channels (labeled C0-C1) 8 channels
Clock/Qual � 2 sections * 4 channels (labeled CLK0-CLK1) 8 channels
Data � 4 sections * 8 channels (labeled D0-D3) 32 channels
GND � 2 GND leads per Address & Control section 16 channels
Total 96 channels

Each of the channel leads has a small crimping mechanism on the end of the wire, allowing easy connection to most devices and components in any circuit.

Configuration
One of the main reasons that this particular logic analyzer is extremely useful is the fact that it is so versatile in the capabilities. The main options you will have to configure before you beginning sampling your data include the following:

- clock sampling rate
- channel selection

As with any computerized machine, the logic analyzer has a set amount of memory, with storage limitations. In order to deal with these limitations we try to achieve an �optimum sampling rate� for our clock, which will take the data from the channel leads and represent it in the output waveforms without using too much memory. The clock rate is the sample of the waveform for the set amount, thus if a clock sample rate is set @ 100ns the analyzer will display a sample of the waveform every 100ns. As a rule of thumb, the clock-sampling rate should be at least 10x smaller than your shortest pulse width in the circuit. This simply allows the output waveforms to have greater accuracy in the portrayal of the actual circuit operation. For example, if we have a circuit that has a characteristic minimum pulse width of 10ms, we should set our clock sampling rate to be at least 10x smaller than this therefore setting the rate at 1ms. At one 1ms, we will achieve 10 samples per pulse width, which essentially means that we will have an extremely accurate waveform, without using too much of the logic analyzers memory to store redundant data. In a mathematical statement, if we have 256kbytes of RAM, and if each sample takes up 64bytes of memory, we will have the following results when viewing our resultant waveforms:

a) Original wave form
b) 256k @ 100ns = 409.6 us worth of sampling
c) 256k @ 10ns = 40.96 us worth of sampling
d) 256k @ 1ns = 4.096 us worth of sampling

a)
b)
c)
d)

Example c) and d) are relatively identical to the original wave form because of the accuracy is increased when the clock sampling rate is increased. The more ideal rate would be c) @10ns because it uses a lot less memory than d) @1ns, therefore more of the total waveform is displayed.
One of the main advantages of the Tektronix analyzer is how well the channel viewing can be configured. Out of the total 96 channels available from the POD, we can select to view as few or as many as needed. Much like the clock sampling rate configuration, we mainly need to select our address leads based on available memory. The 4 main groups of probes coming from the POD are the address, data, control and clock.

Each group should be connected to the appropriate reference point in the circuit being analyzed. The address probes should be connected to the address bus leads in the circuit, the data probes should be connected to the data bus leads, the control probes should be connected into the control bus, and the clock probes being connected to an external clock source. Each group has one ground lead that should be connected to a ground in reference to the point of measurement.

To configure the channel selection, highlight �channel� under the setup title and press the return key. In this screen the analyzer has four titles: Group Name, Input Radix, Probe and Channels. To configure the logic analyzer for optimum memory utilization delete the channels that are not required for output display. Using the arrows in the numeric keys on the keyboard highlight the leads under the �probes� subtitle, which are not in use and the F7 key will delete the unconnected leads. Once all the leads that are not connected are deleted, the sampler will only display the channels that we did not delete and we can return to the main menu to begin the lab.


Logic Analyzer Test

_________, _________ , __________ , _________

a) 10 us
b) 20 us
c) 50 us
d) 2 us

a) �Main Menu�
b) �Select Menu�
c) �MENU�
d) �Return�



a) F7
b) F1
c) �Open/Close�
d) �Rub Out�
a) 8
b) 16
c) 156
d) 96

Lab Exercise

Locate the large machine that looks like a 1970�s supercomputer from 2001 space odyssey with the monitor on it, beside the filing cabinet, that�s looking for a guy name Dave.
Channel option and hit �Return�.

The above steps will ultimately cut down on the number of waveforms displayed once we sample.
Timing.

NOTE: Data Bus not active

The instructions above show to magnify the waveform displays, and modify our clock-sampling rate. Note: To activate the data bus, change the bus switches on the microprocessor trainer to low, then reboot the trainer and re-sample the data by pressing F1.


Lab Test
a) Waveform magnification
b) Display resolution
c) The amount of memory devoted to the output display
d) Dot matrix magnifier
a) F1
b) �Open/Close�
c) F4
d) �Select Menu�
a)GND
b)A0
c)A1
d)D0
a)8
b)16
c)2
d)4
a)Timing
b)Graph
c)Clock
d)Trigger

Answers:
Logic Analyzer Test:
Lab Test:

 Tektronix Digital Logic Analyzer You have completed the report

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Maynard's Logic Analyzer page

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